My General Comments
P4 is a simple language for data plane programming. This makes the p4c backend very complex. Any use of Annotations to hint p4c backend behavior is a cop out. Using Annotations to test a target is reasonable.
Stefan, Google
Agree to dispense with Annotations and use, for example, strings. More details need working out for any clashing namespace, version control for strings, etc.
Tom, Intel
Good that OVS parser is changed to using a P4-like syntax. I think, the first such parsing came out from Stanford U. by Glenn Gibb. See https://github.com/grg/parser-gen/blob/master/examples/headers-datacenter.txt
I think the P4 parser leverages Glenn's paper and parser.
Other parts of the presentation with acceleration needs are similar to Pensando's presentation at the April 2020 RoundTable Series.
Steve, Stanford U.
P4-16 does support connecting pipe(s) via the Package. Connected pipelines exist in the packages in v1model.p4 and psa.p4. An extern such as checksum can be inserted in the pipeline as well. It's complicated pipelines such as deparser feeding back to parser, or event-driven pipes that needs definitions in code. Folks already spoke of GUI and Java to look for event-driven languages/framework. A short video shows more choices.
https://www.youtube.com/watch?v=KX6j0jGEd5Q
Han's mention of P4FPGA uses a proprietary Bluespec compiler which companies have to pay $10k to get the compiler. Only universities get the compiler free. What Xilinx has for P4 FPGA compiler works. An extern is defined using Verilog. One could also use UC/Berkeley's Chisel to define an extern block for FPGA. The Chisel compiler converts the Chisel+Scala code to Verilog and FPGA synthesis.
Vladimir, Barefoot Academy
Got to do better than using Annotations. Using "#ifdef" in production code is a no-no. Who writes the base P4 production-quality code for L2/L3? The code could be checked in to p4c repo in an existing or new directory.
Need to think more for how to specify any object in extern for the control-plane. There is additional complexity in deciding sub-language because a FPGA uses Verilog to specify an extern API while an asic uses P4 or C/C++.